1. Field of the Invention
The present invention relates to a clock generating circuit and a semiconductor device including the same, and more particularly relates to a clock generating circuit that generates, similarly to a DLL (Delay Locked Loop) circuit, a phase-adjusted internal clock signal, and a semiconductor device including the same. The present invention also relates to a data processing system including such a semiconductor device.
2. Description of Related Art
In recent years, a synchronous memory that performs operations in synchronization with a clock has been widely used for a main memory of a personal computer or the like. Specifically, in a DDR (Double Data Rate) synchronous memory, because an input data and an output data need to be synchronized correctly with respect to an external clock signal, it becomes necessary to provide a DLL circuit that generates an internal clock signal that is synchronized with the external clock signal (see Japanese Patent Application Laid-open No. 2005-292947).
The DLL circuit includes a counter circuit in which a count value is updated based on phases of each of the internal clock signal and the external clock signal, and a delay line that generates the internal clock signal by delaying the external clock signal based on the count value of the counter circuit. Updating of the count value is continued even after the DLL circuit is locked so as to follow the external clock signal. That is, an updating operation of the count value is continued even after the internal clock signal has attained a predetermined phase (generally, zero phase) with respect to the phase of the external clock signal. Thus, certain power is continuously consumed even after the DLL circuit is locked.
A semiconductor device that stops power supply to a DLL circuit during a refresh operation is described in Japanese Patent Application Laid-open No. 2004-273106. An internal clock signal that is an output of a DLL circuit is not used any way during the refresh operation. Therefore, when the power supply to the DLL circuit is stopped during the refresh operation, power consumption at least during the refresh operation can be reduced.
However, when the power supply to the DLL circuit is stopped, the count value of a counter circuit is disadvantageously reset. Therefore, the DLL circuit cannot be accessed until the DLL circuit is relocked after the power supply to the DLL circuit is restarted, and this leads to a decrease in the performance of the semiconductor device.
Because the operation of the DLL circuit is continued until a refresh command is issued, the power consumption by the DLL circuit cannot be reduced during this period.
Such problems occur not only in DLL circuits but it also commonly occurs in clock generating circuits that generate a phase-controlled internal clock signal.